A 40nm chip just made Nvidia's A100 look 478 times slower

A neuromorphic chip built around phase-change memristors has achieved a computational speedup of up to 478 times over Nvidia's A100 GPU in brain cortex reconstruction tasks, according to a paper published in Science on July 14. Researchers at Peking University and the Chinese Academy of Sciences Shanghai Institute of Microsystems designed the chip, which departs from conventional digital acceleration by using the physical behavior of memory devices themselves to solve neural dynamics equations. The result is a fundamentally different approach to computation, one that could reshape the economics of specialized workloads, as discussed in the trillion-dollar bottleneck in AI infrastructure.

The 40nm chip measures just 0.28 square millimeters. It integrates in-memory computing arrays for matrix operations and step-drift arrays for adaptive integration, achieving a single-iteration latency of 2.12 milliseconds. This is the first time neural dynamics hardware has pushed below the millisecond threshold in a single iteration, allowing applications that previously could only run offline to operate in real time. It's a stark reminder that brute-force parallelism has limits, and architecture can still surprise us, as the team behind Gemma 4 might attest.

Why neural dynamics are hard

Neural dynamics models describe how neural activity evolves over time. They require iterative solving of differential equations. Traditional von Neumann architectures shuttle data between separate memory and processing units, creating bottlenecks that make real-time execution impractical for high-fidelity models. The Peking University team sidestepped this by leveraging the physics of phase-change memristors. It's a classic example of innovation at the hardware-software boundary, not unlike how Photoroom's data pipeline optimized for breadth over beauty.

Phase-change memristors have continuously variable conductance that can be precisely programmed. The researchers mapped the adaptive step-search process required in neural dynamics solvers directly onto the memristors' natural conductance evolution. Rather than run multiple clock cycles for step-size search, judgment, and adjustment, the device performs these tasks through its own physical evolution. The authors call this physics-driven computing.

Multi-level conductance control also lets the same array store neural network weights and perform analog matrix multiplication at the same time, combining memory and computation in a single physical layer.

Raw performance numbers

In experiments, the chip outperformed the most advanced ASIC accelerators by 3.82 to 36.27 times in speed, while consuming only 3.9 to 7.8 percent of the power. The most striking results came from high-fidelity brain cortex surface reconstruction tasks, where the chip outperformed an Nvidia A100 GPU by a factor of 50.38 to 478.18 times. These numbers put the chip in a league of its own for certain workloads, a reminder that specialization matters when general-purpose hardware hits a wall, as SkyPilot's GPU hopping fix showed on the software side.

The chip runs at 50 MHz with 9-stage pipelining. The results show that architectural innovation, not brute-force parallelism, can deliver orders-of-magnitude gains for specialized computational workloads.

From brain models to brain interfaces

Science published a companion perspective article describing the work as a paradigm shift. The implications go well beyond the demonstrated brain modeling application. Millisecond-level neural dynamics opens the door to real-time brain-computer interfaces, brain digital twins for personalized medicine, neural navigation systems for surgery, and intelligent diagnosis of neurodegenerative diseases such as Parkinson's and Alzheimer's. The potential for real-time brain-computer interfaces echoes the kind of integration we're seeing in other domains, like Alibaba's Qwen powering over 150,000 hardware devices.

Traditional neuromorphic chips from Intel (Loihi) and IBM (TrueNorth) focus on spike-based computation, well suited to classification and pattern recognition. The Peking University chip addresses a different niche: continuous-time, iterative solving of differential equations that underpin biophysical neural models. This puts it in a separate category from both conventional GPUs and spiking neural accelerators.

The research was supported by the New Cornerstone Investigator program, the National Key R&D Program, the National Natural Science Foundation, and the Guangdong Key Laboratory of In-Memory Computing Chips.

As the semiconductor industry struggles with the end of Moore's Law scaling, the chip offers a glimpse of an alternative trajectory one where device physics, rather than transistor density, drives performance improvement.